This invention broadly relates to a semiconductor integrated circuit and a semiconductor integrated circuit device.
Generally, an FPGA (Field Programmable Gate Array) has been well-known as a logic semiconductor integrated circuit having a plurality of transfer gates.
Herein, it is to be noted that the FPGA means a gate array type semiconductor integrated circuit in which a user can freely change logic.
Meanwhile, disclosure has been made about the conventional general structure of the FPGA in Japanese Unexamined Patent Publication No. Hei. 9-148440, as illustrated in FIG. 1.
In such a conventional example, variable logic blocks PLB and switch matrixes SMX are alternatively arranged in vertical and lateral directions at a central portion of a chip SUB.
With this structure, the variable logic block PLB can change a logic function while the switch matrix SMX can change a connection state between wiring patterns.
Further, a X-decoder circuit X-DEC and a Y-decoder and writing circuit Y-DEC and WDR, which selects memory cells placed in the variable logic block PLB and the switch matrix SMX to write data signals, are arranged around the variable logic blocks PLB and the switch matrixes SMX.
Moreover, input-output buffer cells IOB are arranged along the periphery of the chip so as to surround these circuits.
The variable logic block PLB includes the transfer gates for changing the logic, memory cells, and inverters for controlling signals given to the transfer gates.
On the other hand, the switch matrix SMX comprises the transfer gates and the memory cells for controlling ON/OFF operations of the transfer gates. Herein, the transfer gate is composed of an n-channel MOS transistor.
Each of the variable logic block PLB and the switch matrix SMX is occupied by the transfer gates with approximately ⅙ of the total number of the transistors.
Referring to FIG. 2, a p-type well 102 is formed on a silicon substrate 101 in a SMX formation region while a p-well 103 is formed in a PLB formation region.
In this event, a MOSFET Qn1 having a gate electrode G1 and source/drain regions 105 is formed in the SMX formation region while a MOSFET Qn2 having a gate electrode G2 and source/drain regions 106 is formed in the PLB formation region.
Further, interlayer insulating films 111 to 115 are deposited on the silicon substrate 101. Moreover, a first layer metal wiring pattern M1, a second metal layer wiring pattern M2, a third layer metal wiring pattern M3, and a fourth layer metal wiring pattern M4 are placed between the interlayer insulating films.
An output signal of the PLB formation region is produced from the drain region of the MOSFET Qn2, and is transmitted to the SMX formation region via the metal wiring patterns M1, M2, and M3.
Further, the signal is sent to the fourth layer metal wiring pattern M4 through the MOSFT Qn1 serving as a switching transistor, and is transmitted to another switch matrix SMX (not shown) via another variable logic block PLB. Herein, the ON/OFF operation of the MOSFET Qn1 is controlled by a memory device, such as, an SRAM.
In such a programmable logic integrated circuit, a plurality of transfer gates are connected to the wiring pattern. However, the transfer gate is structured by the MOS transistor formed on the silicon substrate in the conventional example.
In consequence, the junction capacitance of the transistor parasites to the wiring pattern, and thereby, the wiring pattern inevitably has large parasitic capacitance.
Further, every when the transfer gate is inserted into the wiring pattern, the wiring pattern is pulled down from the third layer and the fourth layer into the substrate surface. Thereafter, the wiring pattern is pulled up to an upper layer.
Consequently, a wiring length becomes long, and parasitic capacitance is more increased with an increase of parasitic resistance.
Further, all transistors including the transfer gates are formed on the same plane in the conventional example. As a result, each of the switch matrix SMX and the variable logic block PLB has a large area.
To this end, the number of the gates, which can arrange for one chip of the FPGA, is reduced so as to restrict an applied system.
Such a problem is not inherent to the FPGA, and is common to various programmable devices which includes a plurality of switches consisting of the transfer gates other than the FPGA.
Moreover, a chip having a learning function, such as, a digital neuron chip LSI, also includes a plurality of transfer gates, and has the above-mentioned problem.
It is therefore an object of this invention to provide an integrated circuit and device which are capable of reducing parasitic capacitance and parasitic resistance for a wiring pattern of an integrated circuit, such as, a FPGA, and of achieving a high speed operation of an integrated circuit having a plurality of transfer gates.
It is another object of this invention to provide an integrated circuit and device which are capable of realizing high density and high integration of an integrated circuit, and of increasing the number of transfer gates.
According to this invention, a semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate.
With this structure, each of the basic cells includes a wire selection portion and a logic gate portion.
Further, the logic gate portion has a MOS transistor.
Moreover, the wire selection portion has a thin-film transistor (TFT) serving as a transfer gate.
In this condition, the wire selection portion is placed over the logic gate portion via an interlayer insulating film.
In this event, the thin-film transistor may be an n-channel enhancement type or an n-channel depletion type thin-film transistor.
Further, a pair of wiring patterns are formed in the interlayer insulating film, and the thin-film transistor is placed between the wiring patterns.
The thin-film transistor preferably comprises any one of a lateral type and a vertical type.
The thin-film transistor may have at least a channel region, and the channel region may be formed by a non-doped polysilicon film.
More specifically, the transfer gate, which can change the connection path between the wiring patterns, is formed on the semiconductor substrate via the insulating film. The junction capacitance of the TFT formed on the insulating film is excessively small in comparison with the bulk-type transistor.
Further, it is possible to arrange the transfer gate between the wiring patterns. Thereby, it is prevented the wiring pattern from being lengthened by inserting the transfer gate into the wiring pattern. Consequently, the parasitic capacitance of the wiring pattern can be more reduced, and further, the parasitic resistance can be lowered also.
Accordingly, the high speed of the circuit operation can be realized by the structuring the transfer gate with the TFT in the logic integrated circuit, such as, the FPGA, in which the transfer gate for switching a plurality of wiring patterns is connected to the wiring pattern.
Further, the transfer gate, which is can change the connection path between the wiring pattern, is formed on the semiconductor substrate via the insulating film, as mentioned above. Consequently, the number of the devices arranged on the semiconductor substrate as the bulk device is reduced, and thereby, the chip area can be reduced also. If the chip areas are identical to each other, the gate number can be increased with the increase of the device number.
Meanwhile, it has been well known that the three-dimensional integrated circuit provides the high integration. However, a part of device has been not conventionally structured by the TFT in the logic integrated circuit, such as, the FPGA. This is because the TFT has a delay operation, a large leak, and a low heat-dissipating characteristic.
Therefore, it has been considered that the logic integrated circuit having high function and high performance can not be realized by using the TFT.
In the meantime, the transfer gate for changing the wiring path in the logic integrated circuit such as the FPGA has the following advantages.
(1) The ratio of the transfer gates for the total device number is equal to about xc2xc to {fraction (1/10.)}
(2) The operation (namely, the ON/OFF operation) is performed only when initialization, such as, power supply introduction, is carried out.
(3) Only limited transfer gates are kept to the conductive state while a large number of transfer gates are kept to the off state.
In the case where the transfer gate having the above-mentioned advantages is realized by the TFT, the disadvantages inherent to the TFT are removed or eliminated as follows.
Namely, the transfer gate is turned on/off only when the initialization, such as, the power supply introduction is carried out irrelevant of the logic operation of the integrated circuit. Consequently, the operation speed will not cause any problems.
Further, the leak current during the off state of the TFT can be suppressed by lengthening the gate length. The size of the transistor can be enlarged by the following reason.
Namely, only a part of the total device is formed as the TFT, and the remaining devices are formed as the bulk type devices. Consequently, the TFT formed at the upper layer of the bulk type device has a margin in area. Even if the integrated circuit is enlarged, the integration thereof will be not reduced.
Meanwhile, when the gate length is lengthened, the operation speed may be lowered. However, the operation speed does not cause any problems in such a TFT used for the application of this invention.
Further, a small number of TFTs are kept to the on state while a large number of TFTs are kept to the off state. Consequently, even when the heat-dissipating performance is degraded in some TFTs, the heat-generation almost does not occur.
Thus, the operation speed of the logic integrated circuit can be increased. Further, the number of the mountable transfer gates can be increased by realizing the high integration and the high density.
As described above, the transfer gate as the switch between the signals can be selectively formed in the three-dimensional form. Thereby, the parasitic capacitance inherent to the wiring pattern can be largely reduced. Consequently, the high-speed operation can be realized in the programmable device or the neuron device.
Further the chip area can be reduced without the increase of the leak current and without the heat generation by the selective three-dimensional form of the transfer gate.
Moreover, the number of the mountable basic cells or neurons per one chip can be increased, and the application range of the programmable device or the neuron device can be widened largely.